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AUIRFR/U4105Z
D.U.T
+
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
+
?
-
Circuit Layout Considerations
? Low Stray Inductance
? Ground Plane
? Low Leakage Inductance
Current Transformer
D.U.T. I SD Waveform
V GS =10V *
D.U.T. V DS Waveform
?
?
-
R G
- ? +
? dv/dt controlled by R G
? Driver same type as D.U.T.
? I SD controlled by Duty Factor "D"
? D.U.T. - Device Under Test
V DD
+
-
Reverse
Recovery
Current
Re-Applied
Voltage
Inductor Curent
Body Diode Forward
Current
di/dt
Diode Recovery
dv/dt
Body Diode Forward Drop
V DD
Ripple ≤ 5%
I SD
*
V GS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET ? Power MOSFETs
V DS
R D
- V DD
R G
V GS
D.U.T.
+
10V
Pulse Width ≤ 1 μs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
V DS
90%
10%
V GS
t d(on)
t r
t d(off)
t f
Fig 18b. Switching Time Waveforms
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